Failsafe fuze-setting system



March 5, 1968 G. w. KINZELMAN FAILSAFE FUZE-SETTING SYSTEM 4 Sheets-Sheet 1 Filed Dec. 12, 1966 5952 x35 lllll l 32; oz; v v mm mm 8 f @222 5 0% I l l ll 3 9w a 2 Q5: a 125 NOE if: v

INVENTOR KINZELMAN l -qh I ATTORNEYS March 5,1968 5. w. KINZELMAN FAILSAFE FUZE-SETTING SYSTEM 4 Sheets-Sheet 2 Filed Dec. 12, 1966 March 1968 G. w. KINZELMAN 3,371,579

FAILSAFE FUZE-SETTING SYSTEM Filed Dec. 12, 1966 4 Sheets-Sheet 5 3% 2K 320 DETECT' 2N2222 QCORE me I March 5, 1968 G. w. KINZELMAN 3,371,579

FAILSAFE FUZE-SETTING SYSTEM 4 Sheets-Sheet 4 Filed Dec. 12, 1966 United States Patent Qfiice 3,371,579 Patented Mar. 5, 1968 3,371,579 FAILSAFE FUZE-SETTING SYSTEM Gerald W. Kinzelrnan, Washington, D.C., assignor to the United States of America as represented by the Secretary of the Army Filed Dec. 12, 1966, Ser. No. 601,240 8 Claims. (Cl. 89-6) This invention relates generally to failsafe fuze-setting systems and more particularly to an improved digital failsafe fuze-setting system.

Prior art electronic fuze setters have generally been of the analog type depending upon an RC timing circuit for setting a fuze. However, analog circuits do not permit the precision in setting which is required in some cases. Consequently, digital fuze-settin systems have been used where precision fuze setting is required. However, it is quite necessary that such a fuze setting system fail safe with an indication both to insure that the required precision setting has been obtained and also to protect personnel in the field when the fuze is mounted on a missile.

Therefore, it is the primary object of the invention to provide an improved digital electronic fuze-setting system incorporating numerous failsafe features.

Another object of the invention is to provide a readout signal which turns on a ready lamp when the fuze has been set to the desired time.

A further object of the invention is to provide a lockout circuit which sets the system to a safe condition and turns on an error lamp if the fuze should be set to a time less than a predetermined minimum time.

A more specific object of this invention is to set the fuze to a safe condition and. turn on the error lamp when any one of a number of errors occurs, such as the fuze timing mechanisms failing to respond to a timing input pulse or the occurrence of an open circuit in most of the components of the system.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings:

FIGURE 1 is a pictorial representation of a fuze-setting system;

FIGURE 2 is a functional block diagram of the improved fuze-setting system of this invention;

FIGURES 3a and 3b are a combined logic and schematic diagram of the fuze-setting system, and

FIGURE 4 is a combined block and schematic diagram of the fuze.

In FIGURE 1, there is shown a pictorial representation of a digital fuze-setting system. A setter includes four push button switches 12 which are operated to set the setter to a desired time. Typical maximum fuze-setting time is 199.9 seconds. The setter accomplishes this with pulses each representing one-tenth of a second. Consequently, the maximum reading in a typical case on the digital display 14 would be 1999, representing 199.9 seconds. In FIGURE 1, the digital reading of 0473 indicates a fuze setting of 47.3 seconds.

Fuze setter 10 also includes a ready lamp 16 which is energized when the fuze has been properly set. Error lamp 18 is energized when the fuze has been improperly set or any number of other errors occur. As mentioned above and described below in more detail, whenever an error occurs, the system is also disabled and the fuze set to a safe condition.

The fuze setter includes a connector 20 which is connected to the fuze setters internal circuits by a cable 22. Connector 20 has three output conductors 24, one of which is located in the center of the connector and the other two of which are spaced at difierent distances from the center conductor. These conductors are designed to engage corresponding concentric conductors 26 formed on the ends of a typical fuze 28. The prongs 30 on connector 20 are designed to fit over the nose of fuze 28 to stabilize the connector while the fuze is being set. Fuze setter 10 contains a battery (not shown) whose circuit is normally open so that no power is applied to the fuze setter circuits, except to a capacitor which is charged so that it can discharge and generate a clear pulse as soon as the connector is applied to the fuze. However, when the conductors 24 engage the concentric conductors 26, the battery circuit is completed and applies power to both the setter circuits and to the fuze circuits. The time setting is selected by the switches 12 and then is digitally transferred by means of stepping pulses, each representing one-tenth of a second, to the fuze which is set to the selected time.

FIGURE 2 is a functional block diagram of the fuze setting system. The setter comprises a four-decade counter 32 including a units decade 34 with a setting switch 36, a tens decade 38 with a setting switch 40, a hundreds decade 42 with a setting switch 44 and a thousands decade 46 with a setting switch 48. The switches in the various decades in the setter are set to the desired fuze time, the decimal number set in the counter being representative of the fuze time in tenths of seconds. The setter is then coupled to the fuze via the connector 20 as illustrated in FIGURE 1. When the connection is completed, power is automatically applied to the setter circuits via a battery contained in the setter, and no separate fuze power supply is required. The fuze counter contains magnetic cores which at this time are also automatically cleared by the setter to a desired initial state.

In a typical case, a multivibrator 49 runs at about 10 kHz. and feeds pulses through a gate circuit 50 and a logic circuit 52 to both setter counter 32 and a fuze S4. The internal circuits of fuze 54 are designed to return a monitor pulse via a line 56 to the logic circuit for every multivibrator pulse processed by the fuze counter except for one (the 1028th in the embodiment illustrated in FIGURES 3 and 4) at a synchronism check time. At that-time, the counter in fuze 54 does not return a monitor pulse, but a synchronism check circuit 58 connected to setter counter 32 provides a suppression signal via line 60 to logic circuit 52 to suppress the error signal which would otherwise be generated it a monitor pulse were missing. The coincidence of the suppression signal and the absence of a monitor pulse indicates that the setter and fuze counters are stepping in synchronism. Logic 52 is also designed such that, it both a fuze monitor pulse and sync check or suppression signal are received at the same time, then an error signal is generated to energize an error lamp 67 and safe the fuze counter, thereby indicating that the counter in fuze 54 is not in synchronism with the setter. Logic 52 also functions to generate the error signal whenever a monitor pulse is not returned to the setter all times except at the synchronism check time.

When setter counter 32 reaches the number selected by the switches 36, 40, 44 and 48, a readout circuit 62 pro duces a signal on line 64 which closes gate 50 to stop the pulsing of the setter and fuze counters and turn on a ready lamp 6-5.

A 1.9-second lock-out circuit 66 is provided so that, if any fuze time less than 1.9 seconds is selected, fuze 54 will be set to a safe condition and error lamp 67 will be turned on. The fuze is also set to a safe condition and an error lamp energized if any one of a number of other errors occur, such as the occurrence of the synchronism check pulse at the wrong time, an open circuit in the components of the system, failure of the magnetic cores utilized in the counters and other circuits in the setter and fuze, etc.

The dashed line 68 indicates that power is not applied to either the setter or the fuze until the connector in FIGURE '1 electrically couples the fuze and setter. Power circuit is then applied to the fuze setter and clear circuit 72 generates a triangular negative pulse which clears all the stages of the fuze counter to a desired initial state and also leaves the setter circuits in a desired cleared or initial state.

The details of a preferred embodiment of the fuze setting system are shown in FIGURE 3. A battery is connected via a lead 82 to a capacitor 84 in the clear generator 86 and via a resistor '87 and a lead '88 to the pin on the connector 92. Battery 80 is also connected via resistor 87 and a lead 89 to a power switch 98. When the setter is electrically connected to the fuze 94 via the connector 92 a circuit is completed from the positive side of the battery through lead 88, pin 90 and the windings 96 in the feedback core shift register in the fuze through the ground connection back to the negative side of the battery, thereby turning on the power switch 98 and activating the :B-{- and V+ terminals of the switch.

The B+ output from a power switch 98 turns on a silicon controlled switch 100 in clear generator 86 and permits capacitor 84 to discharge through the switch and through the primary winding 101 of a transformer 10 2. A pulse is induced in the secondary winding 103 which turns on the NPN transistor 104, thereby closing circuit through another secondary winding 106, the transistor 104, a diode 109 and the clear-set windings 96 in the fuze. A negative triangular clear pulse 110 is produced on lead 112 which is connected to pin 90 of connector 92. Consequently, when the setter and fuze circuits are first connected, clear pulse 110 is generated and fed through the clear-set windings 96 of the magnetic core feedback shift register which forms the fuze counter to clear the counter, i.e. set all the cores to 1. A positive pulse 111 is produced on lead 113 of the clear generator to reset the flip-flops in the fuse setter.

During this time, a capacitor 114 in a set generator 116 is charging towards twelve volts. When the twelve volt level is reached, a zener diode 118 in a converter 120 breaks down and clamps lead 122 to a logic low (L) level of approximately zero volts. Prior to the breakdown of the zener diode, lead 122 is at the logic high (H) level of 3 volts ('B+). This L level acts as a threshold signal to open a gate 124 and let counter drive pulses generated by multivibrator 126 pass therethrough. Gate 124 contains a flip-flop circuit 126 having an input 128, a set output 130 and a reset output 132. The logic of the flip-flop circuit is such that when the input '128 goes from an H voltage level to a low or L level, the outputs change state. If set outputs 130 and 131 are L level they will change to H level, and reset output 132 will change nearly simultaneously from H level to L level. Consequently, out-ofphase drive pulses appear on the outputs 132 and 131, 130.

The train of positive pulses produced on lead 138 is applied to the set generator 116 which produces on its output set pulses 140 which are fed to pin 90 of connector 92 and from there to the clear-set winding 96 of the magnetic core feedback shift register forming the fuze counter. The positive pulse train from gate 124 is also fed via lead 142 to the input of a decimal counter 144 comprising four decades, each of which consists of a five-stage Johnson decade counter and ten NOR gates which provide the decimal outputs. Since the units, tens and hundreds decades are identical in structure, only the details of the units decade 146 are shown. Only the inputs and outputs of tens decade 1148 and hundreds decade 150 are shown. The details of the partial thousands decade 152 are also shown. i

Counter 144 is designed to count backwards to a predetermined Zero position so that the number appearing on the digital display 14 in FIGURE 1 represents the count remaining in counter 144 as far as the internal circuits of the counter are concerned. The advantage of such an ararran ement is that the personnel in the field do not have to calculate the difference between the desired fuze setting and the period of the counter, but merely operate switches 12 until the desired fuze setting appears on the digital display.

Associated with units decade 146 is a switch 154 which is adapted to be connectedto any one of the outputs of the ten NOR gates 156. Switches 158 and 160 perform the same function for the tens and hundreds decades 148 and 150 respectively. A switch 162 provides the same function with respect to thousands decade 152 in that it is adapted to be connected to the individual outputs of the three NOR gates 164. Switch "16 2 also contains other contacts used in preliminary checking of the circuit as will be described in more detail below. 7

Let us now look at the units decade 146 as a typical decade of the decimal counter 144. In addition to the ten NOR gates 156, it includes a five stage Johnson counter 166. The positive driving pulses from gate 124 on lead 142 are applied to the inputs of the five flip-flops forming counter 166. in the cleared initial condition, an L level voltage appears at the set or upper output and an H level at the reset or lower output of each flip-flop.

Looking at NOR gates 156 now, we see that the input 168 of NOR gate 170 is connected to the L or set output 172 of the fifth stage flip-flop 174 and the other input 176 is connected to the L or set output '178 of the first stage flip-flop 180. Consequently, both inputs of NOR gate 170 are at L, and its output 182 is at H. The L and H designations on the various leads indicate the normal or cleared states of the inputs and outputs of the flip-flops, NOR gates and other logical circuits illustrated in FIGURE 3. Therefore, in the cleared state, it can be determined that the NOR gate 170 has an H level on its output 182 whereas all the other NOR gates have an L output level. Decimal numbers appearing within quotation marks adjacent the output terminals of the NOR gates 156 represent the decimal designation of the outputs as far as the truth table for this particular decimal counter '144 is concerned.

On the negative transition of the first drive pulse applied via lead 142 to decimal counter 144, only flip-flop '180 will switch states so that set output 178 is now H and the reset output 184 is now L. By checking the logic of the inputs of the NOR gates 156, it can now be seen that NOR gate 186 will be at an H level and the other NOR gates will be at an L level output. The complete truth table for the outputs of NOR gates '156 is shown in Table I below.

TABLE I Drive Pulse No. Johnson Counter NOR Gag No.

(Clear) 11111 "6 1 01111 5 2 00111 4 3 00011 3 4 00001 2 5 00000 1 6 10000 "0 7 11000 9" 8 11100 8" 9 11110 7 The four switches 154, 158, 160 and 162 are connected through a readout logic circuit 190 whose output lead 192 is normally at an L level but switches to an H level when the count in decimal counter 144 corresponds to the value selected by the four switches. In other words, when the four switches are each set to a NOR output terminal which is at an H level then an H level appears-0n lead 192 which is connected to gate 124. The Hlevel closes the gate and prevents further drive pulses from being applied to lead 140 and thus to the input of the decimal counter 144. Such a condition indicates that the desired count or fuse setting has been set into the counter 144. The H level on lead 192 is applied via a'lead 194to a ready lamp circuit 196 to energize a ready lamp 198, thereby indicating that the desired fuze setting has been obtained.

An advantage of the arrangement of NOR gates and switches is that an H level must appear on the output of a NOR gate to energize the readout circuit. Consequently, if a poor contact or an open circuit occurs in any of the switches, the readout circuit will never be switched to the ready state since as far as the readout circuit is concerned the counter will never have reached the preselected count as determined by the setting of the switches. Consequently, a failsafe feature is provided since an open circuit in the switches or counter circuits will permit the counter to s.ep down to 0019, which is an error condition which itself will close the gate 124.

Let us now look in more detail into logic utilized in readout logic circuit 190. The output of each of the switches 154, 158, 160, 162 is connected through the corresponding one of four inverters 280. Two of the inverter outputs are connected to another NOR gate 202 and the other two are connected to a NOR gate 204. The third input 216 of each NOR gate is connected to the output of a single shot delay circuit 208 whose function will be described in more detail below. The outputs of NOR gates 202 and 204 are connected through an inverter 206 to the input terminal of a flip-flop 210. The reset terminal 212 of flip-flop 210 is left floating and only the set terminal 214 is connected to output lead 192. When counter 144 is at a count other than the value selected by the four counter switches, then the outputs of all the NOR gates 200 are at H, the outputs of the gates 202 and 204 are at L, the output of inverter 206 is at H, and consequently the set output terminal 214 is at an L level, thereby leaving gate 124 open and ready lamp 198 de-energized. However, when counter 144 reaches the count selected by the four switches, all of the inputs of inverters 200 will go to H and, therefore their outputs will go to L. Let us assume that the lead 216 from the multivibrator 208 is also at L. Under these conditions, the outputs of the NOR gates 202 and 204 will both be at H so thatthe output of the inverter 206 switches from H to L thereby tripping flip-flop 210 so that set terminal 214 goes to H and produces the H level on lead 192.

Let us look more closely at the single shot delay circuit 208. Its output lead 216 is normally sitting at an H level. The n'egative drive pulses from the reset terminal 132 of flip-flop 126 are applied via a lead 21-8 to the input of delay circuit 208. The single shot is triggered on the positive transition, i.e. L to H, of the first pulse appearing on lead 218, whereby switching output lead 216 from an H level to an L level. The output waveform is designated 220. NOR gates 202 and 204 are enabled until the waveform 220 drops below the L level to approximately zero volts. The delay provided by the single shot circuit is for the purpose of letting the other circuits in the system settle down before permitting readout, thereby preventing false readout caused by transients in the various circuits. Waveform 220 from single shot 208 is also applied via a lead 222 to comparision circuit 228 which provides monitor pulse checking and synchronism checking.

The fuze counter is designed to return a feedback or monitor pulse 224 for each transfer within the counter feedback shift register except for a predetermined one, which we shall call the synchronism check point. These monitor pulses are applied via a line 226 to comparison logic circuit 228 which includes at its input a Sehmitt trigger 230 whose output lead 232 is normally at an H level. A monitor pulse on line 226 causes the Schmitt trigger output to go from H to a higher level and then return to H again as shown by the waveform 234. This waveform is applied to afiip-fiop 236 whose set output terminal 238 is normally at L and whose reset terminal is normally at H. The outputs are switched during the negative transition of the waveform 234.

The comparison logic 228 has an output lead 240 which is normally at an L level. However, when any one of a number of error signals occurs the level switches to H which closes the gate 124. The errors are a missed monitor pulse, the occurrence of a monitor pulse simultaneously with a synchronism check pulse, the occurrence of a synchronism check pulse at the wrong time, and the stepping of the decimal counter 144 to a count representing a fuze setting of 1.9 seconds.

Looking at the comparison logic 228 in more detail, we see that the synchronism check point occurs after 1028 pulses or when the decimal counter 144 is stepped from an initial count of 3076 to a count of 2048. The logic circuits are actually conditioned after 1027 pulses or at a count of 2049. The 9 units lead 242 is connecled to an inverter 244, the 40 tens lead 246 to an inverter 248, the 0 hundreds lead 250 to an inverter 252, and the 2 thousands lead 254 to an lIIVCBI'tCI 256. The outputs of inverters 244 and 248 are connected as two inputs to a NOR gate 258, and the outputs of inverters 252 and 256 are connected as two inputs to a NOR gate 260. The outputs of the NOR gates 258 and 260 are connected in common to one input of a NOR gate 262 whose other input is connected to a lead 264 which carries the set output train from terminal 130 of flip-flop 126 in gate circuit 124. The output of NOR gate 262 is connected to the input of another flip-flop 266. Consequently, flip-flop 266 and rlip-flop 236 switch in synchronism with each other with possibly a slight phase delay due to the time required for the monitor pulse to be returned from the fuze counter. However, the delay circuit 208 compensates for this delay as will be described below.

The set output 268 of flip-flop 266 and the reset output 270 of flip-flop 236 are connected as two of the inputs to another NOR gate 272. In like manner, the reset output 274 of flip-flop 266 and the set output 238 of flipflop 236 are connected as two of the inputs to a NOR gate 278. The third input to each of the NOR gates 272 and 278 is the one shot delay circuit 208 which is connected via the lead 222. The outputs of the two NOR gates 272 and 278 are connected as two of the inputs of another NOR gate 280 whose other input is from a NOR gate 282, which is the 1.9 second gate. The output of this latter gate is at level L at any count on decimal counter 144 above 0019. The output of NOR gate 280 is connected to an error flip-flop 284 whose reset terminal 286 is left floating and whose set terminal 288 is connected to the lead 240 on which the H level error signal is produced.

When the setting cycle is first begun, counter 144 is cleared to an initial count representing 3076 and then stepped to the synchronism check point which is a count of 2048. Set pulses are also sent to the fuze counter via pin of connector 92. Consequently, between 3076 and 2048, flip-flops 266 and 236 are driven in synchronism with each other so that one of the inputs of each of the NOR gates 272 and 278 is always H and the other L, and the output of error flip-flop 284 remains low.

However, at the 2049th count, the outputs of NOR gates 258 and 260 go to H so that the output of the NOR gate 262 will not change levels on the next (1028th) drive pulse on lead 264 corresponding to acount, of 2048. Consequently, flip-flop 266 will not change state, and its outputs 268 and 274 will be out-of-phase with the outputs 238 and 270 of flip-flop 236 if at this time a monitor pulse 224 is fed back on line 226 to switch flipflop 236. Therefore, one of the NOR gates 272 and 278 will have two L inputs, and when lead 222 goes to L when the single shot delay 208 is triggered, the output of that NOR gate will go to H thereby lowering the out.- put of NOR gate 280 to L and triggering the output 288 of error flip-flop 284 to H. The H lead on output 288 applies an H level on the error lead 240 which closes gate 124 and also energizes the error lamp circuit 290 and safes the fuze counter. Since the fuze counter is designed so that it does not return a monitor pulse at the 1028th drive pulse, the transmission of such a monitor pulse indicates that the two counters are not in synchronism.

Of course, if the setter and fuze counters are in synchronism, no monitor pulse will occur at the count of 2048, and therefore, flip-flop 236 also will not be switched. Consequently, flip-flops 236 and 266 will remain in synchronism and no H error level will appear on line 240.

The flip-flops 236 and 266 and the associated NOR gate logic also provide an H output from error flip-Hop 284 to indicate an error when a monitor pulse is missing from lead 226 for any time other than that at the synchronism check point corresponding to the 1028th pulse. Similarly, if an H level sync check signal occurs at the outputs of NOR gates 258 and 260 at any time other than at the count of 2049 to inhibit switching of NOR gate 262 at the count of 2048, an error signal will also be generated on lead 240. In either of these error conditions, it is seen that flip-flops 236 and 266 are out-of-phase, thereby triggering the error flip-flop 284.

For the safety of field personnel, the fuze should not be set for a time of 1.9 seconds or less. Such a setting could occur from an inadvertent setting of the switches 154, 158, 160 and 162, or else from a failure of setter counter 144 to stop at the selected time, as would occur if a poor contact or open circuit occurred in any of the switch circuits.

NOR gate 282 functions as a 1.9 second lock-out circuit. Its three inputs are normally at an H level since they are connected through inverters 291, 252 and 223 to the (or 4) output of thousands decade 152, the 0 output of hundreds decade 150, and the 1 output of tens decade 148 respectively. Consequently, the output 292 of NOR gate 282 is normally L, and the output of flip-flop 280 is also normally L so that error flip-flop 284 is not turned on.

However, when counter 144 goes from a count of 0020 to 0019, the three inputs of NOR gate 282 fall to an L level, and output 292 rises to H. Consequently, the output of NOR gate 280 goes to L and switches error flip-flop 284 so that its output 288 goes to H to produce an H error level on lead 240, energizing error circuit 290.

Whenever error circuit 290 is energized by the turning on of error flip-flop 284, an error lamp 294 is turned on. Furthermore, a circuit is completed from battery 80, through lamp 294, a transistor 2%, a lead 226, connector 92 and clear-set windings 96 to ground. Consequently, a positive safe pulse 297 is produced on lead 296 and safes the fuze, i.e., sets all cores to a 0 state.

FIGURE 4 is a combined block and schematic diagram of the fuze counter circuits. The set, clear and safe pulses are applied via the lead 90 to the input of a driver circuit 300 whose output lead 302 is connected to the input of the eleven stage magnetic core feedback shift register 304 which forms the fuze counter 306. For every set pulse 140 applied to the input of the counter, except for the pulse corresponding to the synchronism check time at the count 'of 2048, a monitor pulse is produced on lead 226 which is fed to the input of the Schmitt trigger 230 in FIGURE 3. Note that a monitor pulse is generated on lead 226 every time a bit is shifted between stages due to the charge of the output capacitor on each stage. However, when a bit from stage shifts to stage 11, and there is no hit stored in any other stage, no monitor pulse is produced on the lead 226 since the input circuit of stage 11 is not connected to lead 226. This condition of the shift register corresponds to the synchronism check time.

Let us look more at this operation of counter 306. A set pulse 140 applied to lead 90 is fed to driver circuit 300 and flows through a winding 310 on a core 312, there by setting the core. The pulse is also fed along lead 302 through an EXCLUSIVE OR circuit 313 to the clear-set windings 96 of counter 306. and the clear-set winding 314 on a detect core 316. Any stage core storing a bit will change state and charge its output capacitor, e.g. capacitor 318 in stage 2. Each output capacitor, except in stage 10, is connected through the next stage input winding to lead 226, which in turn is connected through a diode 320 and a lead 322 to the collector of a transistor 324. Transistor 324 remains nonconducting until the magnetic flux of core 312 collapses. The output capacitors can only discharge slowly through the bleed resistor 326 shunting transistor 324. However, the negative transition of set pulse permits the flux of core 312 to collapse. The induced voltage in winding 3Z8 forward biases transistor 324 and renders it conducting. Consequently, each charged capacitor will discharge through the next stage input winding (winding 33%) in stage 2), lead 322, Winding 321, diode 320 and transistor 324, thereby transferring all stored bits, and generating a monitor pulse on lead 226.

However, the truth table of the illustrated core feedback register counter 306 is such that, when it is cleared to an initial state or count of 1029, all stages will be storing a bit. At the 1028th input pulse (count of 1), no monitor pulse will be applied to lead 226 since the input winding 332 of stage 11 is connected through a lead 334, a winding 336, a diode 338, and lead 322 to the collector of transistor 324. However, because there is no connection between winding 332 and lead 226, no monitor pulse appears on the 1028th input pulse.

Both counters 144 and 306 may be considered as backwards counters since the count remainingafter the ready lamp is turned on is equal to the fuze setting. Table II shows the relationships between the input pulses and the counts of particular fuze and setter counters illustrated in FIGURES 3 and 4.

TAB LE II Input Pulse No. Setter Counter Fuze Counter 1 Clear. 2 No monitor pulse. 3 Firing output.

Note that feedback line 340 and feedback line 342 are fed back from core stages 9 and 11, respectively, through the magnetic core EXCLUSIVE OR circuit 313 which forms the input circuit for the shift register. The feedback connections and the EXCLUSIVE OR cause the core register to function similarly to a ring counter having a period of 2047 counts.

When a safe pulse 297 is generated, all the cores in the shift register are set to 0 or safe, because the safe pulse is either held up sufficiently long to permit the output capacitors to discharge slowly through bleeder resistor 326 or else decay-s so slowly that the rate of change of flux in winding 310 is insufficient to induce in winding 328 a voltage high enough to turn on transistor 324. Consequently, allcapacitors are discharged and no hits are transferred between the stages of the fuze counter.

The fuze setter counter and its fail safe and lamp circuits may be checked for operation prior to actual use. The following truth TableIII shows the states of the ready lamp 198 and error lamp.294 for various positions of the setter counter switches t I TABLE III Switch Ready Error 162 160 158 154 0 2 0 ON OFF E1 0 2 0 OFF ON E2 0 2 0 OFF ON 0 0 1 9 ON ON 0 0 1 8 OFF ON The switches 154, 158, 160 and 162 of counter 144 are first set at a count of 0020. When a fuze is set, the table indicates that the ready lamp should be ON and the error lamp OFF.

In row 2, switch 162 grounds the input 232 of flip-flop 236, and does not permit the flip-flop to switch. When an attempt is made to set the fuze, the operation simulates a fuze which does not return a monitor signal. Flip-flops 236 and 266 become out-of-phase and the error lamp turns ON. Since the counter 144 does not satisfy the switch setting the ready lamp should be OFF.

In row 3, the operation is similar to that described for row 2, except that now the comparison logic operates as if counter 144 is not receiving pulses.

In row 4, the switches are set to 0019. The fuze is set to this count and, since the counter satisfies the switch setting, the ready lamp turns ON. The counter also energizes the 1.9 second lockout and turns the error lamp ON, thereby safing the fuze.

In row 5, the switches are set to 0018. When the fuze is set, the 1.9 second lockout turns the error lamp ON before the counter has satisfied the switches, and the ready lamp remains OFF.

The above preliminary checking procedure assures that the ready and error circuits themselves are operative before using the setter to set a fuze.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. A failsafe fuze-setting system comprising:

(a) a fuze setter comprising:

(1) a setter-counter, (2) means to read out said counter when a predetermined count is stored therein, and

(3) a count comparison means connected to said setter-counter,

(b) a fuze comprising:

(1) a fuze counter, and (2) means connecting said fuze counter to said count comparison means, and

(c) means for applying count pulses simultaneously to said fuze setter and to said fuze, whereby said count comparison means is operative to produce an error signal when said counters are not in synchronism.

2. A failsafe fuze setting system as defined in claim 1 further comprising means responsive to a stored count corresponding to a predetermined minimum fuze setting for producing an error signal.

3. A failsafe fuze setting system as defined in claim 1 further comprising means to render said comparison means operative only after a fixed number of count pulses.

4. A failsafe fuze setting system as defined in claim 3 further comprising means responsive to said comparison means to disable said fuze counter upon the occurrence of an error signal.

5. A failsafe fuze setting system as defined in claim 1 further comprising means responsive to said readout means to produce a ready signal and disable said applying means when said predetermined count is stored in said setter-counter.

6. A failsafe fuze setting system as defined in claim 5 further comprising means for preventing said readout means from producing a ready signal if said predetermined count is not stored in said counter.

7. A failsafe fuze setting system as defined in claim 1 wherein said fuze setter further comprises:

(a) a normally open-circuited power source, and

(b) connector means electrically coupled to said setter and adapted to be electrically coupled to said fuze so that power is applied to said setter, and said fuze is energized only when said connector means is electrically coupled to said fuze.

8. A failsafe fuze setting system as defined in claim 1 further comprising means for checking the condition of said means for producing said ready and error signals.

No references cited.

SAMUEL W. ENGLE, Primary Examiner. 

1. A FAILSAFE FUZE-SETTING SYSTEM COMPRISING: (A) A FUZE SETTER COMPRISING: (1) A SETTER-COUNTER, (2) MEANS TO READ OUT SAID COUNTER WHEN A PREDETERMINED COUNT IS STORED THEREIN, AND (3) A COUNT COMPARISON MEANS CONNECTED TO SAID SETTER-COUNTER, (B) A FUZE COMPRISING: (1) A FUZE COUNTER, AND (2) MEANS CONNECTING SAID FUZE COUNTER TO SAID COUNT COMPARISON MEANS, AND (C) MEANS FOR APPLYING COUNT PULSES SIMULTANEOUSLY TO SAID FUZE SETTER AND TO SAID FUZE, WHEREBY SAID COUNT 